As of 1996, the most advanced production-line silicon semiconductor circuit manufacturing processes use 0.35 micron technology, meaning that the minimum size of any circuit feature is 0.35 microns. This, in turn, requires the tools used to measure semiconductor device features to be accurate to approximately 0.035 microns. Production of devices with minimum feature sizes of 0.25 microns, 0.18 microns and less will be likely to take place within by 2001, and production of devices with 0.07 micron sizes is predicted to take place by 2010. However, it is not yet clear what metrological tools will be used to preform the measurements of such devices necessary to develop and accurately model the associated manufacturing processes. SEMs can generally be used to perform measurements with accuracy on the order of 0.05 microns. However, it would appear that SEM technology has been pushed to its limit. Further improvements in the accuracy of SEM based measurements of semiconductor devices are likely to be too limited to perform the metrology required for supporting semiconductor devices using feature sizes of 0.18 microns or less. The manufacture of integrated circuits is a complicated and expensive process sometimes involving dozens of process steps. To ensure that this manufacturing effort is not wasted, steps of the IC fabrication process modeled in process simulators to determine beforehand whether resulting device features will have the desired width, thickness, cross-sectional profile, etc.
Results generated by process simulators, such as PROLITH/2.sup.TM and SAMPLE.sup.TM are typically verified through scanning electron microscope (SEM) examination of a cross section and feature widths of a photolithographically defined surface. However, while SEM verification is adequate for relatively large-scale features (i.e., a few microns and up), SEMs are generally not able to capture critically important cross-sectional details of features defined by submicron photolithography. One reason for this is that SEMs charge the sample under examination with electrons, which has the effect of blurring edges on photographs taken of the imaged surface. While blurring is not a significant problem for surfaces with macroscopic features, it tends to obliterate submicron details. Another problem with SEM metrology is that, typically, IC feature sizes are determined by direct measurement of the SEM photographs with a precision ruler.
Besides the obvious problem of making measurements from the blurred edges described above, direct measurement can result in additional errors due to (1) incorrect placement of the ruler on the edge of a photographed feature (assuming the feature edge is identifiable) and (2) the difficulty of measuring the pitch or angle of a cross-sectional feature with a ruler. In the case of submicron devices, these errors can amount to a significant percentage of the feature being imaged. Additionally, SEMs can physically alter the device features being measured.
Other aspects of process models in need of verification include basic process variables such as the developing rate associated with a particular developing solution. By developing a semiconductor wafer in stages and measuring the change in surface profile after each stage, developing rates can be better quantified, resulting in a more accurate process model. However, given the above mentioned measurement errors associated SEM surface imaging, it is not possible to accurately quantify such process variables using SEM metrology.
Moreover, given the inherent lack of reliability (i.e., reproducibility of measurements) of SEM metrology as applied to submicron features, it is not possible to use SEM measurements to iteratively adjust the process simulator to model better the results of a particular IC manufacturing process. That is, the SEM is better suited to rough verification of a model rather than incremental improvement of a model.
Finally, given the current lack of a reliable method for verifying and updating process models with respect to submicron IC device features, it is not currently possible to modify IC manufacturing/processing steps in accordance with the predictions of an improved process simulator. Consequently, there is a need for an IC process model verification system that incorporates a measuring device that can accurately measure the cross sections of submicron device features. There is also a need for a measuring device that can measure surface profile changes during the performance of semiconductor processing steps.